A Novel Design of SET-CMOS Half Subtractor and Full Subtractor
نویسندگان
چکیده
منابع مشابه
A Novel Design of SET-CMOS Half Subtractor and Full Subtractor
Single Electron transistor have high integration density, ultra-low power dissipation, ultra-small size, unique coulomb blockade oscillation characteristics which makes an attractive technology for future low power VLSI/ULSI systems. The Single Electron Transistor have extremely poor driving capabilities so that direct application to practical circuits is a yet almost impossible, to overcome th...
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In this paper we are presenting a Half-Subtractor using Adaptive Voltage Level (AVL) technique consuming less power than the conventional one .The main objective is to design that half subtractor using either of the two adaptive voltage level(AVL) techniques to reduce the sub threshold leakage current which plays a very important role in the reduction of power dissipation. We can bring down the...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2015
ISSN: 0975-8887
DOI: 10.5120/20032-2134